The present invention relates to a peak-holding circuits which is used for burst communication and provide the detected maximum input signal voltage as an output signal and, more particularly, to a peak-holding circuit for burst communication, which has a quick resetting function and a highly accurate peak-holding function and is obtainable by providing slight additional means to a MOS semiconductor integrated circuit.
In the burst communication, the maximum or minimum level of an input signal which varies with time is usually detected and held for a predetermined period of time. To this end, the peak-holding circuit should have a quick follow-up property for quickly following up the input signal level, as well as ensuring low hold error, i.e., being capable of holding the detected level without being lost by such cause as natural discharge. Furthermore, the peak-holding circuit should have a quick resetting function, that is, it should be able to immediately detect a new input signal. In order to meet these requirements, there have been proposed various peak-holding circuits for burst communication.
FIG. 4 shows a peak-holding circuit according to a prior art circuits.
This peak-holding circuit comprises a differential amplifier 10 having a normal phase input terminal 1, to which an input signal S1 is coupled, and an opposite phase input terminal, to which an output signal from an output terminal 2 is coupled, a forward diode 20 for passing the output of the differential amplifier 10, a holding capacitor 30 for holding the maximum level of the output that is passed, and a buffer 40 for making the maximum level to be an output signal while feeding back the maximum level to the differential amplifier 10.
A short-circuiting switch 50 is provided in parallel with the holding capacitor 30 such that it can be turned on by a reset signal S3. The short-circuiting switch 50 and the holding capacitor 30 are grounded at their terminals opposite the diode 20.
The normal peak-holding function is provided by turning off the short-circuiting switch 50. When the level of the input signal S1 is increased in this state, the diode 20 is turned on to cause current into the holding capacitor 30. The charging is continued until the levels of the differential amplifier output and the input signal become equal.
The terminal voltage across the holding capacitor 30 is detected by the buffer as a voltage level with respect to the ground, and constitutes an output voltage of the peak-holding circuit.
With subsequent level reduction of the input signal S1 the diode 20 is turned off, whereby the holding capacitor 30 holds the charge therein to hold the maximum level of the input signal S1.
For newly detecting the input signal S1, the holding capacitor 30 is discharged with the short-circuiting circuit 50 turned on in response to the input of a reset signal S2 thereto, thus resetting the maximum level that has been held and becoming ready for holding the next maximum level. Where the short-circuiting switch 50 is of MOS semiconductor so that it is low in price and consumes low power for carrying current, the holding capacitor 30 is discharged with a time constant, which is determined by the conduction resistance R50 of the short-circuiting switch 50 when current is carried thereby and the capacitance C30 of the holding capacitor 30.
In this case, time T necessary until the discharging up to 99% of the capacitance C30 is roughly given as: EQU T=5.times.R50.times.C30 (1)
It will be seen that for realizing the above quick resetting function it is necessary to set the conduction resistance R50 and/or the capacitance C30 to be low.
The quick resetting function will be considered in detail by using an example.
The capacitance C30 of the holding capacitor 30 is usually 10 to 1 pF!, and is assumed here to be 10 pF!.
When it is also assumed that the holding capacitor 30 holds a voltage of 1 V! across it and is discharged in 50 nsec., the resistance R50 is 1 k.OMEGA.! from equation (1).
In order to realize this conduction resistance R50 of 1 k.OMEGA.!, in a recent 0.7 .mu.m! semiconductor process, for instance, a gate width of approximately 50 .mu.m! is required as the transistor size, and in this case the gate-drain parasitic capacitance C50 is usually approximately 0.005 pF!.
When the quick resetting function is to be realized in a MOS semiconductor integrated circuit by using a prior art peak-holding circuit for burst communication, however, the following problems are encountered.
In the first place, the charge Q50 that is withdrawn from the holding capacitor 30 for charging the parasitic capacitor C50 when releasing the reset signal, is given by equation (2) given below, and is 0.025.times.10.sup.-12 Coulombs when the supply voltage VDD is 5 V. EQU Q50=C50.times.VDD=0.005.times.10.sup.-12 .times.5 (2)
When the charge Q30 is accumulated in the holding capacitor 30, the above hold error E with respect to this charge Q30 is thus given by equation (3) given below. For example, assuming that the minimum voltage held across the holding capacitor 30 is 10 mV, the charge accumulated at this time is 0.1.times.10.sup.-12 Coulombs. In this case, the hold error E is 25% at the maximum and cannot be ignored. EQU E=Q50/Q30=0.025.times.10.sup.-12 .times.5 (3)
Secondly, in order to reduce the conduction resistance R50 of the short-circuiting switch 50, it is necessary to increase the size of the MOS semiconductor transistor of the switch. By increasing the transistor size, however, the gate-drain parasitic capacitance C50 is also increased, so that the hold error E is increased by noise based on the parasitic capacitance C50 at the time of the switching.